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10.7 Gbps Electro-Absorption Modulator Driver
Preliminary Technical Data
FEATURES
Data Rates up to 10.709Gb/s Typical Rise/Fall Time 27ps Power Dissipation 900mW (at 2V swing, 1V offset) Programmable Modulation Voltage up to 3V Programmable Bias Offset Voltage up to 2V Voltage-input control for offset, modulation Cross Point Adjust Range 30%- 85% Selectable Data Retiming PECL/CML Data & Clock Inputs 50 on Chip Data & Clock Terminations Modulation Ebnable/Disable |S11|<-10dB , |S22|<-8dB at 10GHz Positive or negative 5.2 or 5.0V single supply operation Available in dice and 4x4mm 24 Lead LFCSP package
ADN2849
PRODUCT DESCRIPTION
The ADN2849 is a low power 10.7Gbps driver for electroabsorption modulator (EAM) applications. The modulation voltage is programmable via an external voltage up to a maximum swing of 3V when driving 50. The bias offset voltage and output eye cross point are also programmable. Onchip 50 resistor is provided for back termination of the output. The ADN2849 is driven by AC coupled differential CML level data and has selectable data retiming to remove jitter from data input signal. The modulation voltage can be enabled or disabled by driving the MOD_ENB pin with the proper logic levels. It can operate with positive or negative (5.2V or 5.0V) supply voltage. The ADN284949 is available in a compact 4x4mm plastic package or dice format.
APPLICATIONS
SONET OC-192 Optical Transmitters SDH STM-64 Optical Transmitters 10Gb Ethernet IEEE802.3 XFP/X2/XENPACK/MSA-300 Optical Modules
CPAP CPAN MOD_SET BIAS_SET
GND R R
GND VTERM MODN_TERM
ADN2849
50
DATAP DATAN VBB CLKP CLKN
50 50
MODP MUX D Q CROSS POINT ADJUST
50 50 VEE
VEE
CLK_SELB
MOD_ENB
Figure 1. Functional Block Diagram Rev. Pr. G August 2004
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADN2849 Specifications
Preliminary Technical Data
(Electrical Specifications (VEE=VEEMIN to VEEMAX . All specifications Tmin to Tmax, ZL=50 unless otherwise noted. Typical values specified at 250C)
Table 1.
Parameter Bias Offset Voltage(MODP) Bias offset voltage BIAS_SET voltage to bias offset voltage gain Bias offset voltage drift over temperature and VEE Modulation Voltage(MODP) Modulation voltage swing MOD_SET voltage to modulation voltage swing gain Modulation voltage drift over temperature and VEE Back termination resistance Rise time (20% - 80%) Fall time (20% - 80%) Random jitter Total jitter Cross point adjust range Cross point drift over temperature and VEE Minimum output voltage(single ended) |S22| Modulation enable time Modulation disable time Data Inputs (DATAP, DATAN) Differential Input voltage Termination resistance Setup time (see figure 2) Hold time (see figure 2) |S11| Clock Inputs (CLKP, CLKN) Differential Input voltage Termination resistance |S11| Cross point adjust (CPAN, CPAP) Input voltage range CPAP, CPAN differential voltage Input current Logic Inputs (MOD_ENB, CLK_SELB) VIH VIL IIL IIH Supply VEE IEE
Min -0.25 0.9 -5 0.6 1.5 -5 40
Typ
Max -2.0 1.1 5 3.0 1.9 5 60 36 36 0.75 10 85 5
Unit V V/V % V V/v % ps ps ps RMS psp-p % % V dB ns ns mVp-p ps ps DB mVp-p dB V Vp-p A V V A A A V mA
Conditions Note 1 Ta=250C, VEE=-5.2V
Note1 Ta=250C, VEE=-5.2V
27 27
30 -5 VEE+1.7 -8
Note1 At 10GHz
100 100 600 40 25 25 -10 600 40 -10 -0.85 85 VEE+2 VEE+0.8 -400 20 200 -4.75 -5.2 52 -5.5 -1.85 0.6 115 1600 60 1600 60
CLK_SELB='0' CLK_SELB='0' At 10GHz
At 10GHz
VI=VEE+0.4V VI=VEE+2.4V VI=0V IMOD=0 VMODP/MODN=0
Notes: Minimum supply voltage and minimum output voltage determine maximum output swing and maximum bias offset that can be achieved concurrently. Measured using the characterization circuit shown in figure 3.
Rev. Pr. G | Page 2 of 17
Preliminary Technical Data
SETUP tS HOLD tH
ADN2849
DATAP/N
CLKP/N
Figure 2. Setup and hold time
Figure 3. High-speed characterization circuit
Rev. Pr. G | Page 3 of 17
ADN2849 ABSOLUTE MAXIMUM RATINGS
Table 2.
Preliminary Technical Data
Parameter
VEE to GND VBB to GND DATAP, DATAN to GND CLKP, CLKN to GND CPAP, CPAN to GND MOD_SET to GND BIAS_SET to GND MOD_ENB to GND CLK_SELB to GND Staorage temperature range
Min
TBD TBD TBD TBD TBD TBD TBD TBD TBD -60
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD +150
Units
V V V V V V V V V 0 C
Conditions
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
PACKAGE THERMAL SPECIFICATIONS
Table 3. PARAMETER J-TOP J-PAD MIN TBD TBD TYP TBD TBD MAX TBD TBD UNITS 0 C/W 0 C/W CONDITIONS/COMMENTS Thermal resistance from junction to top of package Thermal resistance from junction to bottom of exposed pad
ORDERING GUIDE
Table 4. Model ADN2849ACP ADN2849ACP-RL ADN2849ACP-RL7 ADN2849SURF
Temperature range -400C to +850C -400C to +850C -400C to +850C -400C to +850C
Package description 24 Lead LFCSP 24 Lead LFCSP 24 Lead LFCSP Bare die
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. Pr. G | Page 4 of 17
Preliminary Technical Data
ADN2849
000
TYPICAL PERFORMANCE CHARACTERISTICS (TA=250C, VEE=-5.2V)
000 000
ALL CAPS (Initial cap ) ALL CAPS (Initial cap )
000
000
000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
000
000 000
000 000
Figure 4. Rise time vs. Swing
Figure 7. Total jitter vs. Swing
000
000
000
ALL CAPS (I niti al cap ) ALL CAPS (I niti al cap )
000
000
000
000
TBD
000 000 000 000 000 ALL CAPS (Initial cap)
000
TBD
000 000 000 000 000 ALL CAPS (Initial cap)
000
000
000 000
000 000
Figure 5. Fall time vs. Swing
Figure 8. Cross point vs. differential voltage at CPAP/CPAN pins
000
000
000 000
ALL CAPS (Initial cap ) ALL CAPS (Initial cap )
000
000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000 000
000 000
000 000
Figure 6. Random jitter vs. Swing
Figure 9. Differential S11 vs. frequency
Rev. Pr. G | Page 5 of 17
ADN2849
000 000
Preliminary Technical Data
000
ALL CAPS (Initial cap ) ALL CAPS (Initial cap )
000
000
000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
000
000 000
000 000
Figure 10. Single-ended S22 vs. frequency
Figure 13. Electrical eye diagram (2.5V swing, 0.5V offset, PRBS31 at 10.7Gbps)
000
000
000
ALL CAPS (I niti al cap )
000
ALL CAPS (Initial cap )
000
000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
TBD
000 000 000 000 000 ALL CAPS (Initial cap)
000
000
000 000
000 000
Figure 14. Optical eye diagram using the FLD5F20NP EML (Pav=0dBm, ER=10dB, PRBS31 pattern at 9.95328Gbps, SONET OC192 mask test)
Figure 21. Total supply current vs. Swing with retiming disabled
000
000
ALL CAPS (Initial cap )
000
000
TBD
000 000 000 ALL CAPS (Initial cap) 000 000
000
000 000
Figure 12. Total supply current vs. Swing with retiming enabled
Rev. Pr. G | Page 6 of 17
Preliminary Technical Data
ADN2849
PIN CONFIGURATION AND FUNCTION DESCRIPTION
BIAS_SET CPAP VTERM CPAN VEE GND
GND DATAP DATAN VBB CLKP CLKN
1
VTERM GND
ADN2849
MODP MODN_TERM GND VEE
M OD_ENB
MOD_SET
CLK_SELB
Figure 15. Pin configuration
Note: There is a n exposed pad on the bottom of the package that must be connected to the most negative supply rail of the ADN2849
Table 5. Pin number 1, 10, 11, 14,17, 20 2 3 4 5 6 7 8 9 12, 13, 21 15 16 18, 19 22 23 24 Exposed Pad
Mnemonic GND DATAP DATAN VBB CLKP CLKN MOD_ENB CLK_SELB MOD_SET VEE MODN_TERM MODP VTERM BIAS_SET CPAP CPAN Pad
GND
GND
Rev. Pr. G | Page 7 of 17
VEE
Description Positive power supply AC coupled CML data, positive differential terminal AC coupled CML data, negative differential terminal CML termination resistor AC coupled CML clock, positive differential terminal AC coupled CML clock, negative differential terminal Modulation enable logic input Retiming select logic input Modulation voltage set input Negative power supply Termination resistor for MODN Positive modulation voltage output Back termination voltage output Bias offset voltage set input Cross point adjust positive control input Cross point adjust negative control input Connect to the most negative supply rail of the ADN2849
ADN2849 PAD CONFIGURATION AND FUNCTION DESCRIPTION
25 24 23 22 21 20 19 19
Preliminary Technical Data
1
18 17
2 3 4 4 5 6
16
ADN2849
15 14 13
26 7
8
9
10
11
12 27
Figure 16. Pad configuration (Die size 2.05x2.05mm, single bond pad size 84x84m with 76x76m glass opening, double bond pad size 184x84mwith 176x76m)
Notes: 1. The metallization photograph and the die pad coordinates appear at the end of this document. 2.The pads that have the same number must be bonded together. 3. The back side of the die must be connected to the most negative supply rail of the ADN2849
Table 6. Pad number 1, 10, 11, 14,17, 20, 25, 26, 27 2 3 4 5 6 7 8 9 12, 13, 21 15 16 18, 19 22 23 24
Mnemonic GND DATAP DATAN VBB CLKP CLKN MOD_ENB CLK_SELB MOD_SET VEE MODN_TERM MODP VTERM BIAS_SET CPAP CPAN
Description Positive power supply AC coupled CML data, positive differential terminal AC coupled CML data, negative differential terminal CML termination resistor AC coupled CML clock, positive differential terminal AC coupled CML clock, negative differential terminal Modulation enable logic input Retiming select logic input Modulation voltage set input Negative power supply Termination resistor for MODN Positive modulation voltage output Back termination voltage output Bias offset voltage set input Cross point adjust positive control input Cross point adjust negative control input
Rev. Pr. G | Page 8 of 17
Preliminary Technical Data
ADN2849
GND
THEORY OF OPERATION
GENERAL
Figure 17 shows a typical EA modulator characteristic. Vm represents the voltage across the modulator and Pout represents the optical output power. For small voltages across the modulator it is in its high transmission state. As the voltage becomes more negative, the modulator becomes less transparent to the laser light. Fig. 17 also shows a typical drive signal for an EA modulator. It consists of a modulation signal with a swing Vs, and a bias offset voltage Vb
Pout
DATAP/CLKP
VEE GND
DATAN/CLKN
VEE
VEE GND
50
50
VBB
Vm
VEE VEE
Figure 18. Equivalent circuit for the data and clock input pins
Vs Vb
Figure 17. Typical transfer function of an EA modulator
As shown in the functional block diagram (figure 1), the ADN2849 consists of an input stage for data signals, a cross point adjust block and the output stage that generates the bias offset and modulation voltages. The retiming option allows the user to reduce the jitter by applying a reference clock to the clock inputs of the ADN2849. The cross point adjust block predistorts the data signal applied to the output stage in order to compensate for the non-linear transfer function of the EA modulator as shown in figure 17. The modulation and the bias offset voltage can be programmed via external DC voltages applied to the ADN2849. These voltages are converted to currents internally and applied to the output stage. The singleended output stage provides both the bias offset and modulation voltages at the same pin (MODP) without the need of any external components. The ADN2849 can operate with positive or negative (5.0V or 5.2V) supply voltage.
The data and clock input pins are internally terminated with a 100 differential termination resistor to minimize signal reflections at the input pins that could otherwise lead to degradation in the output eye diagram. The ADN2849 input pins must be AC-coupled with the signal source to eliminate the need of matching between the common mode voltages of the data signal source and the inputs stage of the driver. Also, the common mode terminal of the internal termination resistors (VBB) must be externally decoupled. Figure 19 shows the recommended connection between the data/signal source and the ADN2849 input pins.
50
50
C DATAP/CLKP C DATAN/CLKN VBB
ADN2849
INPUT STAGE
The input stage of the ADN2849 gains the data and clock signals applied to the DATAP, DATAN and CLKP, CLKN pins respectively to a level that ensures proper operation of the ADN2849's output stage. The data and clock inputs are PECL/CML compatible and can accept input signal swings in the range of 600mV to 1600mV peak-to peak differential. The equivalent circuit for the data and clock input pins is shown in figure 18.
C GND
Data/clock signal source
Figure 19. AC-coupling the data/clock signal source to the ADN2849 input pins
Rev. Pr. G | Page 9 of 17
ADN2849
The capacitors used AC-coupling and the decoupling of the VBB pin must have an impedance less than 50 over the required operating frequency range. Generally this is achieved using values from 10nF to 100nF. The retiming feature of the ADN2849 allows the user to remove the data dependent jitter present on the DATAP and DATAN pins by applying the data and clock signals to the ADN2849's internal latch. The retiming feature can be enabled or disabled depending on the logic level applied to the CLK_SELB pin as described in table 7. Note that any jitter present on the CLKP and CLKN pins is added to the output.
Preliminary Technical Data
CROSS POINT ADJUST
The cross point adjust function allows the user to move the eye crossing level in the modulation voltage to compensate for asymmetry in the EA modulator electrical-to- optical transfer function. Figure 21 shows an example on how the cross point adjust can compensate the asymmetry of the EA modulator transfer function. The 50% cross point in the optical eye can be obtained in this case by moving the cross point of the signal applied to the EA modulator away from the 50% point.
Optical Output
Table 7. CLK_SELB logic level High Low
Retiming function Disabled Enabled
If the retiming feature is disabled the CLKP and CLKN inputs can be left floating. The CLK_SELB is a 5V TTL and CMOS compatible digital input. Its equivalent circuit is shown in figure 20.
Electrical Input
GND
GND
60K 180K
Figure 21. Cross point adjust compensation
CLK_SELB
40K
The cross point is controlled by the differential voltage applied to the CPAP and CPAN pins. The equivalent circuit of the CPAP and CPAN pins is shown in figure 22.
GND
VEE
CPAP 100
VEE
VEE
Figure 20. Equivalent circuit of the CLK_SELB pin
CPAN
GND VEE
100
VEE
100A
100A
VEE
VEE
VEE
Figure 22. Equivalent circuit of the CPAP and CPAN pins
Rev. Pr. G | Page 10 of 17
Preliminary Technical Data
The single-ended voltage at CPAP and CPAN pins must be within the -0.8V to-1.85V range for proper operation of the cross point adjust block. The cross point will be controlled by the differential voltage obtained from the single-ended voltages applied to CPAP and CPAN pins. A simple implementation of a cross point adjust circuit is shown in figure 23 where a 20K potentiometer generates the required differential voltage within the specified input voltage range.
GND
ADN2849
The MOD_ENB pin is a 5V TTL and CMOS compatible logic input. Its equivalent circuit of the MOD_ENB pin is shown in figure 24.
GND GND 180K MOD_ENB 40K
GND 60K
20k
CPAP
CPAN
VEE
Cross Point Adjust
100uA
100uA
VEE
VEE
VEE
Figure 24. Equivalent circuit of the MOD_ENB pin
Figure 23. Cross point adjust control circuit
An alternative implementation is to use a voltage DAC and a single-ended to differential conversion amplifier such as the AD138 that will allow digital control of the cross point. When designing the circuitry that will drive the voltages at the CPAP and CPAN pins the user should take in account that each pin is sinking 100. If the cross point adjust feature is not required both the CPAP and CPAN pins should be connected to GND. This will automatically set the cross point to 50%. Once the cross point adjust has been calibrated under nominal conditions it has very low drift over temperature and supply voltage variations.
OUTPUT STAGE
The output stage of the ADN2849 can provide up to 2V bias offset and up to 3V modulation voltage across a single-ended 50 load. Both the bias offset and the modulation voltage are made available at a single pin (MODN) eliminating the need for external bias inductors as shown in figure 25.
GND
VMOD_SET
MOD_SET
BIAS_SET
GND
MODULATION ENABLE
The modulation voltage generated by the ADN2849 can be enabled or disabled under the control of the MOD_ENB pin. When the modulation is disabled, the input data is ignored and the voltage at the output of the ADN2849 will place the EA modulator in a high absorption (low transparency) state. The relationship between the logic state of the MOD_ENB input and the modulation voltage is described in table 8.
Table 8. MOD_ENB logic level Low High Modulation voltage Enabled Disabled
MODN_TERM
+ -
VBIAS_SET
+ -
100nF
VTERM
ADN2849
GND R R
50
EAM
50
From cross point adjust block
IMOD
MODP
VEE
Figure 25. Output stage of the ADN2849
Rev. Pr. G | Page 11 of 17
ADN2849
Modulation voltage
The modulation voltage is established by switching the modulation current through the parallel combination of the modulator terminating impedance (50) and the 50 backtermination resistor on the ADN2849. The modulation set voltage applied to the MOD_SET pin is converted into current (IMOD) using a voltage-to-current converter which forces a voltage equal to VMOD_SET across an internal fixed resistor. For IMOD range of 24mA to 120mA, the MOD_SET voltage ranges from 340mV to 1.7V. With its maximum modulation current of 120mA, the ADN2849 is capable of generating a 3V modulation voltage across the equivalent load resistance (25). The equivalent circuit of the MOD_SET pin is shown in figure 26.
BIAS_SET GND
Preliminary Technical Data
VTERM MODN_TERM
50 10K MODP VEE
100
VEE GND VEE 5K
GND
100
VEE
Figure 27. Equivalent circuit of the BIAS_SET, MODP, MODN_TERM and VTERM pins
MOD_SET 100
VEE VEE
Figure 26. Equivalent circuit of the MOD_SET pin
During factory calibration of the optical transmitter, the user adjusts the BIAS_SET and MOD_SET voltages to achieve the desired bias offset and modulation voltages. This adjustment calibrates out BIAS_SET to bias offset voltage and MOD_SET to modulation voltage gain variations in the ADN2849 due to resistor process variations and the offset of the internal amplifiers. The drift in the bias offset and modulation voltages over temperature and supply voltage variations is very low once it has been calibrated under nominal conditions.
Headroom calculations Bias offset voltage
The bias offset voltage is set by adjusting the voltage between the BIAS_SET pin and GND. An internal operational amplifier sets the termination voltage for the internal 50 output backtermination resistors (VTERM) by gaining up the BIAS_SET voltage by two. This gain of two cancels out the attenuation of the dividing network formed by the 50 back- termination resistor from the ADN2849 output and the 50 load termination, providing a nominal gain of one from the BIAS_SET input to the bias offset voltage available at the output of the ADN2849 (MODP pin). For proper operation, an external low ESR 100nF decoupling capacitor is required between the VTERM pin and GND to prevent transient disturbances on this node. The equivalent circuits of the BIAS_SET, MODP, MODN_TERM and VTERM pins are shown in figure27. The ADN2849 is capable of delivering up to 2V bias offset and up to 3V modulation voltage on a 50 single-ended load. However, these values for the bias offset and modulation voltages cannot be obtained at the same time due to headroom constraints. The minimum supply voltage and the MODP minimum output voltage specifications determine the maximum modulation and bias offset voltages that can be achieved concurrently. In order to guarantee proper operation of the ADN2849, the bias offset and modulation voltages must satisfy the following condition:
VModulation + VBias Offset VEE - VMODP min
Where, VModulation = the required modulation voltage VBias Offset = the required bias offset voltage VEE = the supply voltage VMODPmin = the minimum voltage at the MODP pin (see table 1)
Rev. Pr. G | Page 12 of 17
Preliminary Technical Data
POWER DISSIPATION
The power dissipated by the ADN2849 is a function of the supply voltage and the level of bias offset and modulation voltages required. Figure 28 shows the power dissipation of the ADN2849 vs. modulation voltage for different bias offset voltages. To ensure long-term reliable operation, the junction temperature of the ADN2849 must not exceed 1250C.
ADN2849
For improved heat dissipation the module's case can be used as heat sink as shown in figure 29. A compact optical module is a complex thermal environment, and calculations of device junction temperature using the package J-A (Junction-toAmbient thermal resistance) do not yield accurate results.
000
000
ALL CAPS (Initial cap )
000
000
TBD
000 000 000 000 000 ALL CAPS (Initial cap)
000
000 000
Figure 28. Power dissipation of the ADN2849 vs. bias offset and modulation voltage
Thermal Compound
Module Case
Die
TTOP
Package
PCB
TJ
Thermo-couple
TPAD
Copper Plane
Filled Vias
Figure 29. Typical optical module structure
Rev. Pr. G | Page 13 of 17
ADN2849
The following procedure can be used to estimate the IC junction temperature. TTOP = Temperature at top of package in 0C. TPAD = Temperature at package exposed paddle in 0C. TJ = IC junction temperature in 0C. P = Power disipation in W. J-TOP = Thermal resistance from IC junction to package top. J-PAD = Thermal resistance from IC junction to package exposed pad.
Preliminary Technical Data
TTOP and TPAD can be determined by measuring the temperature at points inside the module, as shown in fig. 30. The thermocouples should be positioned so as to obtain an accurate measurement of the package top and paddle temperatures. Using this model the junction temperature can be calculated using the formula:
TJ =
P x ( J - PAD x J -TOP ) + TTOP x J - PAD + TPAD x J -TOP J - PAD + J -TOP
Where J-TOP and J-PAD are given in table 3 and P is the power
dissipated by the ADN2849 obtained from the graph shown in figure 28.
TTOP
J-TOP
TTOP
TJ
P J-PAD
TPAD TPAD
Fig. 32. Electrical model for thermal calculations
Rev. Pr. G | Page 14 of 17
Preliminary Technical Data
ADN2849
the CLKP and CLKN pins must be made using 50 transmission lines. The cross point can be adjusted using the potentiometer R3. The modulation voltage can be enabled or disabled using the MOD_ENB pin. The ADN2849 can operate with positive or negative (5.0V or 5.2V) supply voltage. Care should be taken to connect the GND pins to the positive rail of the supply voltage while the VEE and the exposed pad to the negative rail of the supply voltage.
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 31 shows the typical application circuit for the ADN2849. Applying DC voltages to the BIAS_SET and MOD_SET pins can control the Modulation and bias offset voltages. The data signal source must be connected to the DATAP and DATAN pins using 50 impedance transmission lines. If a reference clock signal is available, the retiming option can be enabled using the CLK_SELB input. Note that the connection between the clock signal source and
BIAS_SE T JP1 R4 C 15 GND JP2 R3 GND BIAS_SET VEE C18 C13 GND GND
GND GND C1 J1 J2 GND C2 GND C3 J3 J4 GND C4 GND Z0 =50 GND GND Z 0 =50 GND
CPAN CPAP GND DATAP
VEE
GND VT ERM VT ERM
50
GND Z 0 =50
Z0 =50 C7
DATAN VBB
U1 ADN2849
GND MODP MODN_TE RM GND VE E
EAM
GND CLKP Z 0=50 CLKN
GND C11
MOD_ENB CLK_SELB M OD_SE T GND GND VEE
GND -5.2V GND GND VE E C5 GND C6 M OD_ENB CLK_SELB C12 GND
C10
VEE MOD_SET
Figure 31. Typical ADN2849 application circuit
PCB LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2849 operates, care should be taken when designing the PCB layout in order to obtain optimum performance. It is recommended to use controlled impedance transmission lines for the high-speed signal paths The length of the transmission lines must be kept to a minimum to reduce losses and pattern dependant jitter. All the VEE and GND pins must be connected to solid copper planes using low inductance connections. When the connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. The
VTERM, VBB, MODN_TERM and VEE pins must be locally decoupled with high quality capacitors. If proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each GND pin. A 20F tantalum capacitor must be used as general decoupling capacitor for the entire module The exposed pad should be connected to the most negative rail of the supply voltage using filled vias so that solder does not leak through the vias during reflow. Using filled vias under the package greatly enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow.
Rev. Pr. G | Page 15 of 17
ADN2849
DESIGN EXAMPLE
This section describes a design example that covers the followings: * * Headroom calculation for the required bias offset and modulation voltages Required voltage range at the BIAS_SET and MOD_SET pins to generate the required bias offset and modulation voltages
Preliminary Technical Data
MOD_SET voltage range
The voltage range at the MOD_SET pin to generate 2V bias offset voltage at the MODP pin can be calculated using the MOD_SET voltage to bias offset voltage gain specification from table1 using the formulae:
VMOD _ SET min = VMOD _ SET max =
VMODULATION K max VMODULATION K min
This design example assumes a -5.2V supply voltage, 0.5V bias offset voltage and 2V modulation voltage.
Where Kmin and Kmax are the minimum and maximum values of the MOD_SET voltage to offset bias voltage gain from table1. Substituting the values the MOD_SET voltage range is 1.05V to 1.33V.
Headroom calculations
In order to operate properly, the bias offset and modulation voltages must satisfy the following condition:
VModulation + VBias Offset VEE - VMODP min
Assuming that VMODPmin=1.7V (see table1), the above condition became:
2.5V 5.2 - 1.7 = 3.5V
BIAS_SET voltage range
The voltage range at the BIAS_SET pin to generate 0.5V bias offset voltage at the MODP pin can be calculated using the BIAS_SET voltage to bias offset voltage gain specification from table1 using the formulae:
VBIAS _ SET min = VBIAS _ SET max =
VBIAS OFFSET K max VBIAS OFFSET K min
Where Kmin and Kmax are the minimum and maximum values of the BIAS_SET voltage to offset bias voltage gain from table1. Substituting the values the BIAS_SET voltage range is 0.45V to 0.55V.
Rev. Pr. G | Page 16 of 17
Preliminary Technical Data
ADN2849
OUTLINE DIMENSIONS
4.0 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
19 18 24 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95
6 7
TOP VIE W
3.75 BSC SQ
BOT TO M V IEW
13 12
0.25 MIN 2.50 REF
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 32. 24-Lead Lead Frame Chip Scale Package (LFCSP) 4mmx4mm Body (CP-24) Dimensions shown in millimeters
Figure 33. ADN2849 metallization photograph
Table 9. Die pad coordinates Pad Number 1 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 19 20 21 22 23 24 25 26 27
X(m) -920.50 -920.50 -920.50 -920.50 -920.50 -920.50 -920.50 -609.10 -457.30 -305.50 -103.70 324.85 584.00 920.50 920.50 920.50 920.50 920.50 920.50 628.00 501.10 349.30 182.40 3.50 -457.30 -609.10 -736.00 -736.00 738.00
Y(m) 685.00 331.55 103.05 -48.75 -220.15 -371.95 -525.55 -920.50 -920.50 -920.50 -920.50 -920.50 -920.50 -688.20 -484.20 -271.10 274.50 490.00 694.00 920.50 920.50 920.50 920.50 920.50 920.50 920.50 920.50 -920.50 -920.50
Note: The coordinates are measured between the center of the die and the center of the pad. Rev. Pr. G | Page 17 of 17
PR04323-0-9/04(PrG)
PIN 1 INDICATOR

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